Since the variation in threshold voltage VT of a MOS transistor (MOST) increases along with the miniaturization, the operation speed of the MOSTs in a chip further varies. This variation in speed becomes more pronounced as the operation voltage VDD thereof decreases. Therefore, the MOST with small variation in VT has been desired for the low-voltage operation. FIG. 9B is a graph shown in “Low Power SRAM Menu for SOC Application Using Yin-Yang-Feedback Memory Cell Technology”, by M. Yamaoka et al., Symp. VLSI Circuits Dig., pp. 288-291, June 2004 (Non-Patent Document 1), and as shown in FIG. 9B, the standard deviation σ of the variation in VT increases along with the miniaturization of the bulk MOST. In FIG. 9B, σint represents the standard deviation of a so-called intrinsic VT determined by the variation in the number of impurity atoms in a channel of the MOST and the variation in the position thereof, and σext represents the standard deviation of a so-called extrinsic VT determined by the variation in the size of a channel and the like. The entire variation σ in VT is determined by both the variations. Even in the 90-nm process technology, σ is as large as about 30 mV. Since it is necessary to make a design with taking into account the VT variation (ΔVT) of about 5σ in one chip, the value becomes as large as 150 mV.
Therefore, the effective gate voltage of each MOST in a chip expressed by VDD−(VT0+ΔVT) largely varies. Here, VT0 represents an average VT. Since this gate voltage is almost proportional to the load driving current of the MOST, for example, assuming that VT0 is 0.3 V and ΔVT is 150 mV, the driving current of the MOST rapidly decreases when VDD becomes 1 V or less, and the driving current becomes 0 and the circuit delay time becomes infinite when VDD becomes 0.45 V. The VT variation as described above also increases the offset voltage (difference in VT in paired MOSTs) of a sense amplifier used for a dynamic random access memory (DRAM), which makes the sensing operation unstable.
The variation in speed and the instability of operation due to the miniaturization and the voltage reduction as described above can be suppressed by using a fully-depleted SOI (SOI (Silicon On Insulator) having a fully-depleted double gate structure) (hereinafter, referred to as FD-SOI) MOST. The detailed structure and characteristics of the SOI MOST are described in “Silicon on Thin BOX: A New Paradigm of The CMOSFET for Low-Power and High-Performance Application Featuring Wide-Range Back-Bias Control”, by R. Tsuchiya et al., IEDM Dig. Tech. Papers, pp. 631-634, December 2004 (Non-Patent Document 2).
The structure shown in the Non-Patent Document 2 will be schematically described below. FIG. 9A shows a sectional view and an equivalent circuit diagram of an N channel MOST (NMOST) and a P channel MOST (PMOST). A gate G is a gate electrode formed of a metal silicide film such as NiSi, a channel forming area just below the gate is a thin film made of single crystal semiconductor (SOI layer), D or S is a P type or N type high-concentration ultrathin drain or source diffusion layer, BOX is a buried oxide layer (BOX layer), an n+ well layer is formed just below the BOX in the PMOST, and a p+ well layer and a deep n well layer (n-Well) are formed just below the BOX in the NMOST, and they are integrated on a p type substrate. The MOST as described above is characterized in that VT thereof can be controlled according to the type of a gate material, the concentration of the well below the BOX layer, and the voltage applied to the well layer as shown in FIG. 9C. In an actual MOST, the channel length (Lg) is 100 nm or less, the thickness of the SOI layer having the MOST formed therein is 20 nm or less, the thickness of the BOX layer is 10 nm or less, and the concentration of its underlying well layer ranges from 1016 cm−3 to 1018 cm−3. As described above, the standard deviation σ of the variation in VT of the MOST is reduced to 20% or less of the conventional bulk structure by the thin BOX layer and others (FIG. 9B). The variation of the intrinsic VT determining the offset of a sense amplifier is reduced to one-tenth or less, that is, to an ignorable level because it is a random variation. The double gate MOST structure can be regarded as one MOST in which an upper MOST and a lower MOST are connected in parallel. In this case, in the lower MOST, the well functions as a gate, and the BOX layer functions as a gate insulator. Therefore, as shown in the example of the NMOST in FIG. 9C, the threshold voltage VT of the entire double gate MOST can be largely changed by changing the well voltage of the lower part. This is because, since the well layer is isolated from others, the well voltage can be largely changed without generating pn junction leakage current.